1. Technical Field
The present invention relates generally to a semiconductor is integrated circuit and a method for driving the same, and more particularly, to a semiconductor memory apparatus having a pre-discharging function, a semiconductor integrated circuit having the same, and a method for driving the same.
2. Related Art
A semiconductor memory apparatus is divided into a volatile memory apparatus which requires constant electronic recharging to preserve its data, and a nonvolatile memory apparatus which retains its data even in absence of power supply. The volatile memory apparatus includes DRAM and SRAM, and the nonvolatile memory apparatus includes flash memory.
DRAM has an advantage in that it has low power consumption and allows a random access. However, since DRAM is a volatile memory, a high charge storage capability may be required. SRAM used as cache memory has an advantage in that it allows a random access and has a high operation speed. However, since SRAM is not only a volatile memory but also has a large size, the cost thereof is high. Furthermore, the flash memory is a nonvolatile memory, but requires a higher operation voltage than an external power supply voltage. Accordingly, a voltage boosting circuit is required to form the operation voltage required for a write/erase operation.
Meanwhile, ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), and phase-change random access memory (PRAM) are being developed as the next is generation of semiconductor memory device.
Among them, PRAM includes a phase-change material having high resistance in an amorphous state and low resistance in a crystalline state, and writes information into the memory device by a phase change of the phase-change material. PRAM has a higher operation speed and a degree of higher integration than the flash memory.
A memory cell of such a phase-change memory apparatus may include a switching element coupled to a word line, a variable resistor formed of a phase-change material which receives current through the switching element, and a bit line coupled to the variable resistor.
Here, a write operation of the phase-change apparatus provides a certain current, for example, from the bit line to a phase-change material of a selected memory cell to change the phase of the phase-change material into a crystalline state or amorphous state, and thus data of 0 (set) or 1 (reset) is written to the phase-change material.
Meanwhile, a read operation of the phase-change memory apparatus is performed by measuring resistance of the phase-change material to which the data of 0 or 1 has been written by the write operation.
Such a phase-change memory apparatus includes a bit line discharge block having a plurality of bit line discharge switches coupled to one ends of the respective bit lines, in order to precisely read and write data. Each of the bit line discharge switches is configured to discharge electric charges stored in the corresponding bit line at the initial stage of an active mode, in response to an active mode signal.
Accordingly, the phase-change memory apparatus needs to discharge the bit lines by sufficiently performing a discharge operation, for example, before a read or write operation. However, due to a time taken to perform the discharge operation, an actual time for performing the read/write operation may decrease to meet a required operation time in a standard. Therefore, a read/write failure of the phase-change memory apparatus may occur.